Scaling Integrated Photonics for the AI Revolution - A Testing Perspective

Introduction

The rapid growth of artificial intelligence (AI) and machine learning applications is driving an insatiable demand for increased bandwidth and computational power. Integrated photonics, which utilizes light instead of electricity for data transmission, offers a promising solution to address this demand. However, as integrated photonic devices become more complex and channel counts increase, testing these devices throughout the product lifecycle poses significant challenges. This article provides an overview of the testing requirements and considerations for scaling integrated photonics to meet the needs of the AI revolution.

Product Life Cycle and Manufacturing Stages

The product life cycle of integrated photonic devices can be divided into several stages, each with its own testing requirements:

1. Development (R&D)

2. Validation (DVT)

3. Manufacturing

   1. Wafer Sort

   2. Die/PIC Assembly

   3. Packaged Test

4. Deployment

During the Development and Validation stages, comprehensive testing is crucial to ensure that all performance parameters, including high-speed characterization, are thoroughly evaluated to guarantee known-good-die. In the Manufacturing stage, testing approaches may evolve as production ramps up, with a focus on reducing test coverage while maintaining statistical sampling to ensure product quality.

Photonics Test Overview

Integrated photonic devices consist of various components, each requiring specific testing procedures. These components include:

• Laser diode

• Ring resonator

• Modulator

• Receiver

• Fiber array

• Waveguides

• Mux/demux

• Grating coupler

Testing requirements can be broadly categorized into four main areas:

1. Passive Testing: Evaluating insertion loss, return loss, wavelength dependence, and polarization dependence.

2. Active Testing: Characterizing fiber array alignment, power levels, optical spectrum, side-mode suppression ratio (SMSR), optical signal-to-noise ratio (OSNR), line width, modulation depth, light-current-voltage (LIV) curve, photocurrent linearity, responsivity, and relative intensity noise (RIN).

3. High-speed Testing: Analyzing eye diagrams, bit error rate (BER), receiver sensitivity, and S-parameters.

4. Module Testing: Ensuring proper functioning of the integrated device within its intended module form factor (e.g., QSFP-DD, OSFP-XD, OIF 3.2T CPO).

A comprehensive test setup typically includes instruments such as tunable lasers, swept or stepped sources, polarization controllers, optical spectrum analyzers (OSAs), optical-to-electrical (O2E) converters, optical power meters (OPMs), signal-measuring units (SMUs), digital storage oscilloscopes (DSOs), continuous-wave continuous-wavelength (CW-CW) sources, error location sources (ELSs), bit error rate testers (BERTs), and laser component analyzers (LCAs).

Parametric Testing: Wavelength and Polarization Dependence

During the Manufacturing stage, particularly in the Wafer Sort and Die/PIC Assembly phases, parametric testing is critical to characterize the wavelength and polarization-dependent behavior of integrated photonic devices. This testing involves:

1. Setting up a wafer handler and a probing system to inject optical signals into the wafer.

2. Powering and activating the devices under test (DUTs).

3. Measuring the optical signal output from the DUTs.

4. Performing high-speed characterization to identify known-good-die.

In the pre-production phase, comprehensive testing covering all performance parameters, including high-speed characterization, is essential to guarantee known-good-die. As production ramps up, test coverage may be reduced based on statistical sampling while still ensuring known-good-die.

Die/PIC Assembly Testing

During the Die/PIC Assembly stage, guaranteed known-good-die from the previous stage undergo fiber array alignment and other assembly steps. The testing objectives include:

1. Optimizing the fiber array position while curing the adhesive between the DUT and the fiber array.

2. Validating that all channels of the DUT are still performing within specifications.

3. Parallel testing for quick screening.

High-yield and low-risk assembly processes may only require validating that all channels are operational, while lower-yield or higher-risk processes may necessitate additional testing.

Packaged Testing

In the final stage of the manufacturing cycle, packaged testing focuses on at-speed optimization and ensuring compliance with specifications over temperature ranges. This testing typically involves:

1. Evaluating the device within its intended module form factor (e.g., QSFP-DD, OSFP-XD, OIF 3.2T CPO).

2. Utilizing test fixtures for DUT control and high-speed signal access.

3. Implementing thermal streaming or thermoelectric cooling (TEC) for temperature control.

4. Fine-tuning device parameters to maximize yield.

In the pre-production phase, comprehensive testing covering all performance parameters over temperature is essential to guarantee product compliance. During high-volume production, test coverage may be scaled down while still ensuring that products meet all requirements, potentially avoiding thermal validation.

Scaling Integrated Photonics Testing

To effectively scale integrated photonics testing for the AI revolution, several key considerations must be addressed:

1. Full Complement of Photonics Test Function: A comprehensive suite of test capabilities is required to address the diverse testing needs across the product lifecycle.

2. Flexible Platform: The testing platform should be adaptable, transitioning seamlessly from R&D to validation, characterization, pilot production, and finally mass production.

3. Integration: Testing solutions must be tightly integrated with wafer probing, assembly, and alignment equipment.

4. Scalability: High-channel-count parallel testing capabilities are essential to accommodate the increasing complexity of integrated photonic devices.

5. High-Density: Compact test solutions that pack a large number of instruments into a small footprint are desirable for efficient testing.

6. Optimized Test Flow: Streamlined test flows are crucial to minimize testing time and associated costs.

7. Standardization: Standardization of optical signal access, measurements, test plans, hardware frameworks, and software frameworks is highly beneficial for seamless integration and scalability.

By addressing these considerations, the integrated photonics industry can effectively scale testing capabilities to meet the unprecedented demands of the AI revolution, enabling the widespread adoption of high-performance, cost-effective integrated photonic solutions.

Reference

[2] K. Propstra, "Scaling Integrated Photonics for the AI Revolution - A Testing Perspective," presented at the Integrated Photonics Ecosystem Series, Jan. 8, 2024.