IMEC Update | Thermal Management Challenges of 3D Integrated Silicon Photonic Circuits

Abstract

This paper investigates the thermal effects of three-dimensional (3D) hybrid integration of electronic integrated circuits (EICs) and silicon photonic integrated circuits (PICs) for high-performance optical interconnects. Dense wavelength division multiplexing PIC architectures with integrated ring-based photonic devices are thermally characterized before and after EIC assembly [1]. Thermal measurements and simulations indicate substantial negative impact on photonic device thermal efficiency and crosstalk due to EIC heat spreading. Strategies are explored to mitigate these effects through thermally aware interface designs between EIC and PIC.

Introduction

The exponential growth in internet traffic has necessitated high bandwidth and energy efficient interconnects. Silicon photonics leverages CMOS fabrication to enable large-scale photonic integration, making it suitable for these high-performance links. However, thermal sensitivity of nanophotonic devices presents reliability challenges. Active thermal control through on-chip microheaters enables stable device operation. Furthermore, photonic-electronic convergence is essential, requiring dense 3D integration of PIC and EIC dies using flip-chip bonding. This 3D stacking introduces additional thermal design complexity impacting photonic device performance.

In this work, thermal measurements and multiphysics simulations are conducted on a test vehicle consisting of a PIC with integrated ring modulators flip-chip bonded to a CMOS EIC. Two key metrics - heater efficiency and thermal crosstalk, are extracted before and after EIC integration. The impact of substrate undercuts around photonic devices is also analyzed. These studies enable a quantitative assessment of the thermal penalties introduced through 3D integration as well as provide a pathway to thermal co-optimization of the photonic-electronic interface.

Figure 1. (a) CPO conceptual drawing. (b) The optical transceiver module consists of a PIC with 3D integrated driver EIC and laser. The EIC-PIC is bonded face-to-face (F2F). The whole assembly has a back-side heat sink and a top-side cold plate. (c) The transceiver utilizes DWDM architecture with ring modulators (d) on the transmit side (Tx) and ring filters on the receive side (Rx), which are tuned with a heater.

Test Vehicle Description

The test vehicle consists of a 5x5 mm2 silicon PIC fabricated in a CMOS pilot line flip-chip assembled to a smaller 1.5x1 mm2 CMOS EIC using an array of Cu-Sn microbumps at 50 μm pitch embedded in epoxy underfill. The PIC transmit side consists of ring modulators with integrated tungsten microheaters for thermal tuning. Two device variants are characterized - with and without a substrate undercut trench surrounding the silicon waveguide. The EIC provides the electronic driver circuits for the photonic devices. Electrical pads and optical grating couplers provide interfaces to the test setup for electro-optic device measurements.

Figure 2. Picture of test vehicle: (a), (b) PIC with electrical driver (EIC) hybrid integrated with flip-chip bonding. Cross-section scanning electron microscope (SEM) picture of (c) 3D die stack and (d) sketch: MH and WG. (e) Finite element mesh.

Experiments and Simulation Methodology

Two key device metrics are thermally characterized by tracking the resonance peak shift of ring modulators - heater efficiency and thermal crosstalk between devices. Heater efficiency denotes the resonance wavelength shift per unit power applied to integrated microheater. Lower heater power for a given wavelength shift indicates better efficiency. Thermal crosstalk represents undesired heating of a ring modulator from an activated neighbor’s heater. These metrics are measured at 25°C before and after flip-chip integration of the EIC to quantify the impact of 3D stacking.

A multiphysics finite element model of the EIC-PIC assembly is constructed with the commercial solver MSC Marc. Joule heating in device microheaters is the simulation input. Convective boundaries, substrate conduction and interface resistances represent packaging effects. Two methods are compared to model the complex microbump interface layer - an actual geometry approach capturing individual bump dimensions and an equivalent property approach with effective conductivities matching the layer cross-section. The waveguide temperature provides the figure-of-merit to assess heater efficiency.

Table 1. Thermal conductivity values for thermal simulations,UF = underfill in μbump layer.

	Si	SiO2	Cu	W	UF	Cu-Sn	BEOL (EIC)
Thermal conductivity [W/(m-K)]	150	1	400	100	0.18	65	1.5

Figure 3. μbumps modeling: individual geometric or with equivalent material properties through unit cell approach. The equivalent out-of-plane thermal conductivity is calculated using the temperature drop across the μbump ΔT = T1 − T2.

Results

1. Heater Efficiency

Experiments indicate a substantial drop in heater efficiency (up to 44%) after EIC integration caused by undesired lateral heat spreading into the EIC acting as a heat sink. This lowers thermal resistance and microheater power efficiency. Both methods for modeling the microbump layer show good agreement with measurements. The EIC presents a parallel path for heat dissipation from PIC devices, offsetting benefits of undercut isolation trenches.

Figure 4. Measurement of the ring modulator heater efficiency.

Table 2. Ring modulator heater efficiency from experiments (pm/mW) and simulations (equivalent model) (K/mW). The value between brackets is obtained by the geometric model.

	No UCUT	UCUT
	No EIC	With EIC	No EIC	With EIC
Experiment (pm/mW)	165	131	312	180
Simulation (K/mW)	3.07	2.14	5.44	2.86 (3.08)
Simulation (pm/mW)	192	134	340	179
Difference (%)	16.3	2.1	8.97	0.55

2. Thermal Crosstalk

EIC integration increases thermal crosstalk between devices by up to 44% due to additional lateral conduction. However, the model indicates inclusion of top-side cooling solutions can reduce long-range crosstalk by 50%. So while the EIC middleware enhances electrical connectivity, it degrades thermal isolation without careful co-optimization.

Figure 5. Thermal crosstalk measurement with UCUT (a) and without UCUT (b). Both results are with EIC integration. Note that the ring modulators with UCUT (a) are designed for O-band operation and without UCUT (b) for C-band operation.

Table 3. Thermal crosstalk experiment and simulation (equivalent model) of EIC-PIC assembly, in percentages.

Distance (μm)	Crosstalk (%)
Experiment	Simulation
No UCUT	UCUT	No UCUT	UCUT
100	2.62	1.65	2.32	1.68
200	2.33	1.43	2.06	1.49
300	1.94	1.32	1.92	1.39

Figure 6. Simulation result: (a) temperature contour plot of ring modulator cross section, (b) without EIC and (c), (d) with EIC integration.

Figure 7. (a) Linear temperature profile through WG and (b) circular temperature profile along the WG circumference.

Figure 8. Measured versus simulated heater efficiency for four cases: with and without UCUT/EIC. Red and orange impact on the heater efficiency with EIC and UCUT is obtained by a thermal modeling study.

Figure 9. (a) Thermal crosstalk measurement and simulation result with EIC. (b) Simulated crosstalk with and without EIC.

Figure 10. (a), (b) Simulated thermal crosstalk for the reference case (test setup) and for a real package case (top-side cold plate)

Mitigation Strategies and Conclusions

The undesirable thermal effects of the EIC heat spreading can be mitigated through thermally aware co-design of the microbump interface and PIC back-end-of-line metallization. Strategies include:

1. Maximizing effective thermal resistance of interface underfill

2. Increasing spacing between microbumps and photonic devices

3. Reducing metallic linewidth of wiring to microbumps

Simulations indicate combining these techniques can potentially recover >75% of the thermal efficiency loss from EIC integration thereby enabling reliable 3D photonic-electronic modules without significant device performance degradation or power penalties.

Figure 11. Heater efficiency versus bond layer thermal resistance.

Figure 12. Effective thermal conductivity of the μbump layer as a function of the underfill thermal conductivity.

Figure 13. Cross section of ring modulator and μbumps, with simulated and normalized temperature contours. (a) the reference design, (b) the adapted design with −50% μbump size, and (c) the increased gap between ring modulator and μbumps.

Figure 14. Simulation result: (a) the heater efficiency as a function of the gap between the ring modulator and μbump. The green data point is obtained for −50% size μbumps at the original pitch (50 μm); see Fig. 13(b). Decreasing μbump size effectively increases the μbump-RM gap. (b) The heater efficiency as a function of the Cu linewidth.

Figure 15. (a) Model showing the ring modulator and 4 × 3 array of μbumps in its close vicinity and increased gap between the ring modulator and its μbumps. (b) Top view of the heat flux through μbumps for the reference case and moved μbumps case.

Conclusion

This work provides a comprehensive thermal analysis and mitigation roadmap for hybrid integrated silicon photonic interconnects - an emerging technological platform for next-generation high-performance computing and data centers. Thermally co-optimized 3D integration of photonic and electronic dies can unlock performance scaling of these heterogeneous systems.

Reference

[1]D. Coenen, M. Kim, H. Oprins, Y. Ban, D. Velenis, J. Van Campenhout, and I. De Wolf, "Thermal modeling of hybrid three-dimensional integrated, ring-based silicon photonic-electronic transceivers," Journal of Optical Microsystems, vol. 4, no. 1, Jan.-Mar. 2024, Art. no. 011004, doi: 10.1117/1.JOM.4.1.011004.