IEDM2024|Advanced Backside Power Delivery Network Technology for CPUs
- Latitude Design Systems
- 3 minutes ago
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Introduction
In the sub-2nm semiconductor technology domain, power delivery network (PDN) design plays a crucial role in the performance of high-performance (HP) and low-power (LP) CPUs. Referring to papers from the IEDM conference, this document analyzes the latest backside power delivery network (BSPDN) technologies, comparing the thermal performance and power integrity characteristics of various architectures [1].

Initially, the basic BSPDN structures are introduced. With technological advancement, various backside power delivery architectures have been proposed to address power delivery challenges in CPUs using advanced processes.


The fundamental differences among these architectures lie in the methods of supplying power to the transistor layers. Each design has unique advantages and challenges concerning manufacturing complexity and electrical performance.
Technical Parameters and Design Considerations
Several critical parameters must be considered when evaluating BSPDN architectures. Contact resistance between power delivery structures and device layers significantly impacts overall performance.

Power density distribution is another critical factor in CPU design. High-performance and low-power applications exhibit significant differences in power requirements.

Thermal Modeling and Analysis
Understanding thermal behavior is essential in evaluating BSPDN architectures. Comprehensive thermal analysis requires detailed modeling of each chip layer.


Thermal modeling includes both package-level and local analysis to capture various thermal effects.


Performance Analysis and Results
Thermal performance analysis reveals intriguing patterns among different architectures.


Temperature variations across different substrate thicknesses provide critical insights for thermal management challenges.


Power integrity analysis demonstrates significant advantages of backside power delivery compared to traditional frontside power supply.

The analysis covers both dynamic and static scenarios, considering operating temperature impacts.


Comprehensive analysis indicates that while BSC technology faces challenges in thermal performance, it excels in power integrity. Meanwhile, the PV architecture provides a balanced solution between thermal and electrical performance. These findings provide essential insights for CPU PDN design in advanced process nodes.
Reference
[1] L. Wang et al., "Power and Thermal Integrity Analysis of High Performance and Low Power CPUs at Sub-2nm Node Designed with Various Advanced Backside PDNs," to be published in 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024.
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