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IEDM2024|Advanced Backside Power Delivery Network Technology for CPUs

Introduction

In the sub-2nm semiconductor technology domain, power delivery network (PDN) design plays a crucial role in the performance of high-performance (HP) and low-power (LP) CPUs. Referring to papers from the IEDM conference, this document analyzes the latest backside power delivery network (BSPDN) technologies, comparing the thermal performance and power integrity characteristics of various architectures [1].

Power and Thermal Integrity Analysis of High Performance and Low Power CPUs at Sub-2nm Node Designed with Various Advanced Backside PDNs

Initially, the basic BSPDN structures are introduced. With technological advancement, various backside power delivery architectures have been proposed to address power delivery challenges in CPUs using advanced processes.

different advanced local BSPDN connection schemes, including BPR+nTSV last
Figure 1 illustrates different advanced local BSPDN connection schemes, including BPR+nTSV last, BPR+nTSV first (slit-nTSV), Power Via, and self-aligned BSC designs developed by major semiconductor companies.
schematic structures of various BSPDN schemes, emphasizing backside power connection contacts and local/global power circuit configurations
Figure 2 provides schematic structures of various BSPDN schemes, emphasizing backside power connection contacts and local/global power circuit configurations.

The fundamental differences among these architectures lie in the methods of supplying power to the transistor layers. Each design has unique advantages and challenges concerning manufacturing complexity and electrical performance.

Technical Parameters and Design Considerations

Several critical parameters must be considered when evaluating BSPDN architectures. Contact resistance between power delivery structures and device layers significantly impacts overall performance.

electrical parameters of local power line components across different BSPDN solutions
Table 1 details electrical parameters of local power line components across different BSPDN solutions, highlighting substantial improvements in contact resistance from BPR to BSC technologies.

Power density distribution is another critical factor in CPU design. High-performance and low-power applications exhibit significant differences in power requirements.

power density distribution for HP and LP&HD CPUs, illustrating significant differences in power demands between these designs
Figure 3 shows power density distribution for HP and LP&HD CPUs, illustrating significant differences in power demands between these designs.
Thermal Modeling and Analysis

Understanding thermal behavior is essential in evaluating BSPDN architectures. Comprehensive thermal analysis requires detailed modeling of each chip layer.

thermal modeling methods for back-end-of-line
Figure 4 presents thermal modeling methods for back-end-of-line (BEOL), including comprehensive BEOL modeling and effective thermal conductivity calculations.
backside interconnect modeling for various architectures, including front-end-of-line (FEOL), BEOL, and thinned silicon substrate implementations
Figure 5 details backside interconnect modeling for various architectures, including front-end-of-line (FEOL), BEOL, and thinned silicon substrate implementations.

Thermal modeling includes both package-level and local analysis to capture various thermal effects.

full-chip modeling method using equivalent layers
Figure 6 illustrates a full-chip modeling method using equivalent layers.
local thermal modeling diagrams for three backside connection architectures
Figure 7 demonstrates local thermal modeling diagrams for three backside connection architectures.
Performance Analysis and Results

Thermal performance analysis reveals intriguing patterns among different architectures.

layer-by-layer temperature distribution for the BPR architecture using a 500nm thinned silicon substrate
Figure 8 visualizes layer-by-layer temperature distribution for the BPR architecture using a 500nm thinned silicon substrate.
vertical temperature profiles from comprehensive thermal modeling with detailed backside interconnects
Figure 9 displays vertical temperature profiles from comprehensive thermal modeling with detailed backside interconnects.

Temperature variations across different substrate thicknesses provide critical insights for thermal management challenges.

maximum temperature in comprehensive thermal modeling for various PDN structures and substrate thicknesses
Figure 10 compares the maximum temperature in comprehensive thermal modeling for various PDN structures and substrate thicknesses.
maximum temperature trends in HP and LP CPU designs relative to silicon substrate thickness
Figure 11 illustrates maximum temperature trends in HP and LP CPU designs relative to silicon substrate thickness.

Power integrity analysis demonstrates significant advantages of backside power delivery compared to traditional frontside power supply.

cumulative probability distributions of IR voltage drops derived from power density map analysis for multiple cycles and BSPDN technologies
Figure 12 shows cumulative probability distributions of IR voltage drops derived from power density map analysis for multiple cycles and BSPDN technologies.

The analysis covers both dynamic and static scenarios, considering operating temperature impacts.

compares the 98th percentile dynamic IR voltage drop in LP and HP CPUs across different PDN technologies
Figure 13 compares the 98th percentile dynamic IR voltage drop in LP and HP CPUs across different PDN technologies.
impact of backside M1 or frontside M1 pitch on dynamic IR voltage drop performance
Figure 14 illustrates the impact of backside M1 or frontside M1 pitch on dynamic IR voltage drop performance.

Comprehensive analysis indicates that while BSC technology faces challenges in thermal performance, it excels in power integrity. Meanwhile, the PV architecture provides a balanced solution between thermal and electrical performance. These findings provide essential insights for CPU PDN design in advanced process nodes.

Reference

[1] L. Wang et al., "Power and Thermal Integrity Analysis of High Performance and Low Power CPUs at Sub-2nm Node Designed with Various Advanced Backside PDNs," to be published in 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024.

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