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IEDM2024|Introduction to Dual-Gap CMOS-MEMS CMUT Arrays

Introduction

The development of capacitive micromachined ultrasonic transducers (CMUTs) has significantly advanced the field of ultrasound transducers. This paper presents a detailed introduction to a novel dual-gap CMOS-MEMS CMUT array, which demonstrates outstanding performance characteristics while maintaining cost-effectiveness.

Design and Implementation of a Novel Dual-Gap CMOS-MEMS CMUT Array
cross-sectional view of the proposed CMUT chip structure along with detailed material layers
Figure 1 illustrates the cross-sectional view of the proposed CMUT chip structure along with detailed material layers.
staggered design and defines geometric parameters of the CMUT array
Figure 2 explains the staggered design and defines geometric parameters of the CMUT array.
Structure and Design

The dual-gap CMUT array incorporates two distinct sensing gaps —180 nm (MIM) and 400 nm (TiN-C)—fabricated using a standard 0.18 µm CMOS process. This innovative design employs different sacrificial layers (CTM and Metal-3) to achieve varying gap distances. The array consists of eight units, each containing 6x27 MIM and 6x27 TiN-C films arranged alternately.

photographs of the dual-gap CMUT array, including optical microscope images and FIB cross-sectional views clearly showing the two gap distances
Figure 3 presents photographs of the dual-gap CMUT array, including optical microscope images and FIB cross-sectional views clearly showing the two gap distances.
Fabrication Process

The fabrication process utilizes TSMC’s 0.18 µm 1-Poly-6-Metal RF CMOS platform. The process begins with piranha solution-based metal trench etching, followed by reactive ion etching to expose sacrificial layers. Removal of aluminum-copper alloy forms the sensing gaps, and PECVD silicon nitride deposition seals these gaps. Final steps involve laser pad openings, metal wire bonding, and parylene C deposition for packaging.

entire fabrication process flow, from unreleased CMOS chips to the final parylene C deposition, clearly illustrating each critical step
Figure 4 details the entire fabrication process flow, from unreleased CMOS chips to the final parylene C deposition, clearly illustrating each critical step.
Performance Evaluation

Device performance was evaluated through multiples tests:

1.Electromechanical Coupling Strength

Using a network analyzer, resonance frequency shifts were measured under varying DC bias voltages to determine the electromechanical coupling coefficient. Narrower gaps showed significantly improved coupling at lower DC bias voltages.

frequency measurement setup and the relationship between frequency shifts and DC bias voltage, including extracted electromechanical coupling coefficients
Figure 5 shows the frequency measurement setup and the relationship between frequency shifts and DC bias voltage, including extracted electromechanical coupling coefficients.

2.Underwater Performance

Underwater testing demonstrated excellent transmission and reception capabilities. MIM CMUT achieved an emission efficiency of 16.7 kPa/V/mm² at a 35 V bias, while TiN-C CMUT displayed higher maximum output pressure capability.

the underwater emission measurement setup
Figure 6 illustrates the underwater emission measurement setup.
measured underwater acoustic pressure levels at varying distances and DC biases, along with reception sensitivity results
Figure 7 displays measured underwater acoustic pressure levels at varying distances and DC biases, along with reception sensitivity results.

3.Self-Emission and Reception Test

To validate dual-gap concept compatibility, self-emission/reception tests were conducted using various transceiver combinations. Results confirmed smooth communication among different devices, validating the dual-gap design methodology.

underwater emission and reception waveforms using different CMUT transceiver combinations, demonstrating successful operation
Figure 8 shows underwater emission and reception waveforms using different CMUT transceiver combinations, demonstrating successful operation.
Circuit Integration and Performance Comparison

All eight CMUT units are integrated with adjustable-gain transimpedance amplifier interface circuits. Integration achieved a noise efficiency factor (NEF) of 0.39 mPa√(mW/Hz), significantly improving over previous designs.

compares reception waveforms with and without integrated amplifiers
Figure 9 compares reception waveforms with and without integrated amplifiers.

The dual-gap CMUT array successfully demonstrates enhanced overall emission and reception efficiencies while maintaining practical advantages of low bias voltage and close-range applications. Integration with monolithically fabricated interface circuits proves excellent signal-to-noise performance under limited power consumption, suitable for advanced ultrasonic sensing and imaging applications.

Reference

[1] H. -Y. Chen, C. T. -C. Nguyen and S. -S. Li, "Design and Implementation of a Novel Dual-Gap CMOS-MEMS CMUT Array," 2024 IEEE International Electron Devices Meeting (IEDM).

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