Monolithic Photonic Dot-Product Engine for Photonic Computing

Introduction

The ever-increasing demand for machine learning (ML) and artificial intelligence (AI) has led to the emergence of photonic computing as a promising alternative to electronic computing. Photonic integrated circuits (PICs) can be used to construct artificial neural network architectures, leveraging the inherent advantages of light such as high speed, wide bandwidth, and energy efficiency. One key operation in neural networks is the dot-product or vector multiplication, which forms the basis for critical functions like convolutions.

This tutorial discusses the design and implementation of a fully integrated photonic dot-product engine monolithically integrated in a 45nm silicon-on-insulator (SOI) CMOS technology from GlobalFoundries, known as 45SPCLO. This technology enables the co-integration of electronic and photonic devices on the same substrate, mitigating challenges associated with separate electronic and photonic chips, such as bandwidth limitations, interconnect complexity, and thermal management issues.

Photonic Dot-Product Engine Architecture

The photonic dot-product engine architecture, as shown in Figure 1, consists of two key photonic components: microring resonators (MRRs) and a balanced photodetector (BPD). The MRRs, resonating at a wavelength of 1310 nm, are used to perform the dot-product operation through intensity modulation. Two switched-capacitor (SC) digital-to-analog converters (DACs) are employed to drive the MRRs with analog signals representing the input vectors.

Figure 1: Architecture (top) and layout (bottom) of the implemented photonic dot-product engine, including electronic and photonic integrated circuits.

The dot-product operation is realized as follows: The input vectors [X] and [Y] are represented by the intensity variations of the input light passing through the on-resonance MRR1 and MRR2, respectively. The through port of MRR1 provides the modulated [X], while the through port of MRR2 provides the dot-product operation of [X]*[Y] after weighting the modulated [X] with [Y].

The through and drop ports of MRR2 are exploited to enable complementary ± weighting. After subtraction of the photocurrent through the BPD, the resulting photocurrent has a linear relationship with the normalized dot-product of [X]*[Y], as shown in Figure 2.

Figure 2: Detected photocurrent of the operated dot-product result.

Switched-Capacitor Digital-to-Analog Converter (SC DAC)

The two 20 GS/s 8-bit SC DACs are responsible for converting the digital input data into analog signals to modulate the MRRs with the required weights of [X] and [Y]. The schematic of the 8-bit SC DAC core is shown in Figure 3.

Figure 3: Switched-capacitor core and inset SC-DAC unit-cell.

The implementation consists of 255-unit cells, each containing an inverter-based latch and driver, and a 0.5 fF metal-oxide-metal (MOM) capacitor. Simulations show that the 20-GS/s 8-bit SC-DAC design achieves a spurious-free dynamic range (SFDR) of 64 dB near the upper limit of the first Nyquist zone, as depicted in Figure 4, while consuming 106 mW from a single 1 V supply.

Figure 4: Output spectra at 20 GS/s with single-tone near-Nyquist.

Transimpedance Amplifier (TIA)

The transimpedance amplifier (TIA) is responsible for converting the photocurrent signal from the BPD into a voltage signal. The implemented single-ended inverter-based TIA is shown in Figure 5.

Figure 5: Simplified block diagram of the TIA.

The TIA consists of two stages: a shunt-feedback inverter and a Cherry-Hooper (CH) post-amplifier. The inverter-based amplifier provides twice the transconductance compared to a common-source differential pair for the same drain current, making it a more energy-efficient choice. The feedback resistor (RF) determines the transimpedance gain and ensures that the inverter is self-biased at approximately VDD/2. The CH post-amplifier provides high-bandwidth voltage amplification.

Frequency domain simulations, shown in Figure 6, indicate that the TIA provides 70.5 dBΩ of gain with 11.7 GHz of bandwidth while consuming 1 mW from a single 1 V supply.

Figure 6: Simulated gain versus frequency showing a bandwidth of 11.7 GHz and a peak gain of 73.5 dBΩ.

Conclusion

This tutorial presented the design and implementation of a fully integrated photonic dot-product engine in 45nm SOI CMOS technology from GlobalFoundries. The photonic elements, consisting of two MRRs and a BPD, perform the dot-product operation through intensity modulation. Two 20 GS/s 8-bit SC DACs modulate the MRRs with the required weights, and a TIA converts the resulting photocurrent from the BPD into a voltage signal.

Simulation results confirm the functionality of the dot-product design, achieving an SFDR of 64 dB for the SC DAC and 70.5 dBΩ of gain with 11.7 GHz of bandwidth for the TIA, while consuming 110 mW from a 1 V supply.

This monolithic integration of electronic and photonic circuits on the same substrate paves the way for high-performance, energy-efficient photonic computing systems, enabling the realization of complex artificial neural networks and other computationally intensive tasks.

Reference

[1] Hassan, S. Saha, and A. Chan Carusone, "Fully Integrated Photonic Dot-product Engine in 45-nm SOI CMOS for Photonic Computing," IEEE Photonics Conference (IPC), 2023.