IEDM2024|TSMC’s Next-Generation SoIC System-Level Chip Integration Platform

Introduction

As semiconductor technology continues to evolve, the demand for high-performance computing (HPC) applications is rapidly increasing. This article explores TSMC’s innovative next-generation system on integrated chips (SoIC) platform, which advances Moore’s law through cutting-edge 3D stacking technology [1].

SoIC Architecture and Process Flow

TSMC’s next-generation SoIC technology is based on a unique chip stacking methodology. Through SoIC bonding, the top chip is connected to the underlying wafer or chip with their device sides facing each other. This configuration enables heterogeneous integration, allowing advanced-process computing chips to be bonded atop mature-process chips containing memory or peripheral circuits.

Figure 1: Process flow diagram of TSMC's new-generation SoIC technology, illustrating key steps from SoC fabrication to final TSV exposure.

Compared to previous generations, this new SoIC technology achieves significant performance improvements:

	Previous SolC Generation	Next SolC Generation
SolC Bonding Density	1.00X	1.83X
Power efficiency	1.00X	1.07X
Bandwidth/power	1.00X	1.96X

Table I: Performance comparison showing notable enhancements in SoIC bonding density (1.83×), power efficiency (1.07×), and bandwidth/power ratio (1.96×).

Advanced Manufacturing and Reliability Features

The manufacturing process incorporates precise yield management techniques. Through meticulous process optimization, this technology significantly increases bonding density while maintaining high yield.

Figure 2: Chart showing the relationship between SoIC bonding density and daisy-chain test yield, highlighting performance improvements from early stages to current benchmarks.

Connectivity reliability has been verified through extensive testing. The technology demonstrated excellent yield statistics across billions of connections:

Figure 3: Yield distribution of daisy-chain continuity tests, based on 760 million SoIC bonding connections on a single wafer.

Thermal management improvements are especially notable:

Figure 4: Bar chart showing reduction in thermal resistance, with new processes lowering the maximum junction temperature by approximately 50%.

Electrical Performance and Integration Capability

The platform’s electrical characteristics have been comprehensively verified through various testing methods. Transistor performance stability has been confirmed before and after SoIC stacking:

Figure 5: Detailed comparison of NMOS and PMOS device characteristics (Isat-Vt and Isat-Ioff), confirming consistent performance pre- and post-SoIC stacking.

The platform also excels in high-performance memory integration:

Figure 6: MBIST results demonstrate SRAM yield and minimum operating voltage (Vmin) for configurations with high current (48.4 MB) and high density (50.0 MB).

Bandwidth and Energy Efficiency Achievements

This platform delivers outstanding bandwidth density performance, establishing a new industry benchmark:

Figure 7: Graph showing the relationship between bandwidth density/energy efficiency and SoIC bonding pitch, with the new technology exceeding >900 Tbps/mm²/pJ/bit.

Reliability and Protection Mechanisms

The platform incorporates robust ESD protection and reliability features:

Figure 8: ESD current distribution showing performance improvements after implementing anti-ESD processes.

Reliability testing includes comprehensive package-level validation:

	Testing Items	Results
Packaging Reliability	MR3X	Pass
TCG2000	Pass
uHAST264	Pass
HTS1000	Pass
SM	TSV SM	Pass
Backside Metallization SM	Pass
SOIC bonding SM	Pass

Table II: Summary of package reliability and stress migration test results, indicating all standard reliability tests have been passed.

Electromigration characteristics have been thoroughly validated:

Figure 9: Electromigration test results of SoIC bonding and backside metallization, confirming compliance with reliability specifications.

Conclusion

The next-generation SoIC technology achieves a significant breakthrough in 3D integration capabilities, delivering superior performance for HPC applications. Comprehensive validation across electrical, thermal, and reliability domains ensures production readiness. Its advanced features set a new standard for chip-to-chip integration in the semiconductor industry.

The successful integration of this technology with TSMC's advanced packaging solutions, and its compatibility with leading process nodes, make it a critical enabling technology for future HPC innovation. As semiconductor integration technologies continue to evolve, this platform lays a solid foundation for next-generation computing solutions.

Reference

[1] Y.-M. Chen et al., "Next Generation TSMC-SoIC® Platform for Ultra-High Bandwidth HPC Application," in 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024.