Chiplet Design and Heterogeneous Integration Packaging

Introduction

The semiconductor industry has identified five major growth engines (applications): mobile, high-performance computing (HPC), autonomous vehicles, Internet of Things (IoT), and big data/edge computing. Advanced packaging technologies play a crucial role in enabling these applications by increasing speed, interconnect density, and power dissipation. This tutorial will explore various advanced packaging technologies, including 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration, with a focus on chiplet design and heterogeneous integration packaging.

Fig. 1 Advanced packaging ranking according to their density and performance

Fig. 2 Groups of advanced packaging: 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration

Flip-Chip Bumping and Bonding/Assembly

Flip-chip bumping is a critical process for advanced packaging. The most widely used bumps are controlled collapse chip connection (C4) bumps and chip connection (C2) bumps, also known as microbumps (μbumps). Figure 3 illustrates the wafer bumping processes for C4 and C2 bumps.

Fig. 3 Wafer bumping: a C4 process and b C2 process. c Amkor’s Double-POSSUM.

C2 bumps, consisting of a copper pillar with solder caps, offer advantages over C4 bumps, including finer pitch capability, better thermal and electrical performance, as shown in Table 1.

Table 1. C4 bumps versus C2 bumps: bump pitch and self-alignment.

	Thermal conductivity (W/m∙K)	Electrical resistivity (pΩ∙m)	Bump pitch	Self-alignment
Cu	400	0.0172	-	-
C4 bump (solder)	55-60	0.12-0.14	≥50 µm	Very good
C2 bump (Cu pillar + solder cap)	300 (effective)	0.025 (effective)	<50 µm	Very poor

Flip-chip bonding/assembly methods include mass reflow, thermocompression bonding (TCB) with low or high force, and bumpless hybrid bonding. Figure 4 depicts these methods.

Fig. 4 Flip-chip assembly and bonding. a Mass reflows of C4 or C2 bumps (CUF). b TCB with low force and reflow of C4 or C2 bumps (CUF). c TCB with high force and reflow of C2 bumps (NCP). d TCB with high force and reflow of C2 bumps (NCF). e Bumpless hybrid bonding.

Hybrid Bonding

Hybrid bonding, also known as direct bond interconnect (DBI), is a bumpless, low-temperature bonding technique that simultaneously forms electrical interconnects and bonds wafers or chips. Figure 5 illustrates the key process steps for DBI.

Sony was the first to use DBI in high-volume manufacturing for its IMX260 backside-illuminated CMOS image sensor (BI-CIS), as shown in Figs. 6 and 7. Other companies, such as TSMC, Intel, SK Hynix, and imec, are also exploring hybrid bonding.

Fig. 5 Key process steps (fundamental) of hybrid bonding. a Metal (Cu) recess = 3 nm plasma surface activation. b Oxide-to-oxide initial bond at room temperature. c Heating closes dishing gap (metal CTE > oxide CTE) (optional). d Annealing (e.g., 300 °C for 0.5 h) w/o external pressure

Fig. 6 Sony’s CMOS image sensor manufactured by hybrid bonding

Fig. 7 Sony’s future CMOS image sensor technology

TSMC's System on Integrated Chips (SoIC) technology, shown in Fig. 8, utilizes bumpless Cu-Cu hybrid bonding for chiplet integration, offering superior electrical performance and higher interconnect density compared to conventional flip-chip technology.

Fig. 8 a TSMC’s SoIC by hybrid bonding. b Electric performance: SoIC hybrid bonding versus conventional flip-chip bonding. c Bump density performance: SoIC hybrid bonding versus conventional flip-chip bonding

Intel's FOVEROS Direct, illustrated in Fig. 9, is a hybrid bonding technology that enables a pad pitch as low as 10 μm and 10,000 bumpless interconnects per mm², surpassing the capabilities of conventional 50-μm-pitch μbump flip-chip technology.

Fig. 9 Intel’s hybrid bonding (FOVEROS Direct): μbump versus bumpless

SK Hynix demonstrated wafer-to-wafer Cu-Cu hybrid bonding for stacking DRAMs, as depicted in Fig. 10.

Fig. 10 SK Hynix’s hybrid bonding of three wafers

2D IC Integration

2D IC integration refers to having at least two chips on the same package substrate or fan-out redistribution layer (RDL) substrate. Figures 11 and 12 provide examples of 2D IC integration, which can be realized through various packaging technologies, such as flip-chip, wire bonding, fan-out with chip-first or chip-last.

Fig. 11 Examples of 2D IC integration. a Two flip-chips on a package substrate. b One flip-chip and one MEMS with wirebonds on a package substrate

Fig. 12 Heterogeneous integration of four chips on a fan-out RDL substrate

2.1D IC Integration

2.1D IC integration involves fabricating fine metal linewidth and spacing (L/S) thin-film layers directly on top of a build-up package substrate or high-density fan-out (HDFO) substrate, as shown in Fig. 13. This enables higher interconnect density and improved electrical performance compared to 2D IC integration.

Fig. 13 Schematics of a 2.1D, b 2.3D, and c 2.5D/3D IC integration

2.3D IC Integration

In 2.3D IC integration, multichips are supported by an inorganic or organic through-silicon via (TSV)-less interposer (substrate) and then attached to a package substrate, as illustrated in Fig. 14. This approach offers higher interconnect density and performance compared to 2D and 2.1D IC integration.

Fig. 14 Shinko’s 2.1D IC integration: i-THOP (integrated thin-film high-density organic package)

2.5D IC Integration

2.5D IC integration involves multichips supported by a passive TSV interposer and then attached to a package substrate, as depicted in Fig. 15. This technology provides higher interconnect density and performance than 2D, 2.1D, and 2.3D IC integration.

Fig. 15 JCET’s 2.1.D IC integration: uFOS (ultraformat organic substrate)

3D IC Integration

In 3D IC integration, multichips are supported by an active TSV interposer and then attached to a package substrate, as shown in Fig. 16. This approach offers the highest interconnect density and performance among the advanced packaging technologies discussed.

Fig. 16 Intel’s EMIB (embedded multidie interconnect bridge) embedded in organic package substrate and Agilex FPGA module

Chiplet Design and Heterogeneous Integration Packaging

Chiplet design and heterogeneous integration packaging provide alternatives to system-on-chip (SoC) designs, especially for advanced nodes. By partitioning the SoC into smaller chiplets optimized for different process nodes and functionalities, and then integrating them through advanced packaging technologies, chiplet designs offer benefits such as improved yield, reduced development costs, and increased flexibility.

Substrates for Advanced Packaging

Different substrates are employed for advanced packaging, depending on the application's requirements for size, pin count, and metal linewidth and spacing. Figure 17 illustrates various substrates used in advanced packaging.

Fig. 17 IBM’s DBHi (direct bonded heterogeneous integration)

Lateral Communication between Chiplets

Lateral communication between chiplets is facilitated by silicon bridges embedded in organic build-up package substrates, fan-out epoxy molding compounds (EMCs), or flexible bridges, as shown in Fig. 18.

Fig. 18 a. Applied Materials’ bridge embedded in EMC by fan-out chip (bridge) first die face-up process. US 10,651,126, 2020. b Unimicron’s bridge embedded in EMC by fan-out chip (bridge) first die face-down process. US 11,410,933, 2022

Fan-In and Fan-Out Packaging

Fan-in packaging, such as six-side molded wafer-level chip-scale packages (WLCSPs), provides a compact form factor, as depicted in Fig. 19. Fan-out packaging, available in chip-first, chip-last, and other configurations, offers higher input/output (I/O) density and better thermal and electrical performance, as illustrated in Fig. 20.

Fig. 19 Examples on bridges embedded in EMC. a TSMC’s LSI (local silicon interconnect). b SPIL’s FO-EB (fan-out-embedded bridge). c Amkor’s S-Connect. d ASE’s sFOCoS (stack Si bridge fan-out chip-on-substrate). e IME’s EFI (embedded fine interconnect)

Fig. 20 SUN Microsystems’ flexible bridge

Low-Loss Dielectric Materials

For high-speed and high-frequency applications in advanced packaging, low-loss dielectric materials are essential. These materials minimize signal loss and enable better electrical performance.

Conclusion

Advanced packaging technologies, including 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration, along with chiplet design and heterogeneous integration packaging, play a crucial role in enabling the semiconductor industry's growth engines. Techniques such as hybrid bonding, fan-in and fan-out packaging, and the use of low-loss dielectric materials contribute to higher interconnect density, improved electrical performance, and enhanced thermal management. As the demand for high-performance computing, autonomous vehicles, and other emerging applications continues to grow, advanced packaging will remain a critical enabler for semiconductor innovation.

Reference

[1] J. H. Lau, Chiplet Design and Heterogeneous Integration Packaging. 1st ed. Singapore: Springer, 2023. [Online]. Available: https://doi.org/10.1007/978-981-19-9917-8