Chiplet Placement Design in 2.5D IC Considering Thermal Effects

Introduction

As Moore's Law approaches its physical limits, the semiconductor industry is shifting toward advanced technologies such as 2.5D and 3D integrated circuits. In 2.5D integration, multiple chiplets are placed on an interposer using micro-bumps, through-silicon vias, and redistribution layers. This architecture offers advantages in heterogeneous integration but also presents challenges in chiplet placement optimization and thermal management [1].

Figure 1: Hierarchical architecture of 2.5D integrated circuits and various interconnect components.

Placement Optimization Framework

The framework consists of two main stages: the first stage optimizes routing length using a sequence pair based tree structure (SP-Tree), and the second stage performs post-placement optimization considering thermal effects. The system first processes input constraints, including fixed outline requirements for the interposer size and the necessary spacing between chiplets. These constraints form the basis for subsequent optimization decisions.

Figure 2: Complete processing flow from input constraints to the final solution.

SP-Tree Based Placement Method

Compared to the previous CSP-Tree method, the SP-Tree method has significant improvements. Its primary advantage lies in its ability to efficiently represent and process placement schemes while eliminating redundant or invalid configurations. This method ensures that all generated placement solutions are physically realizable.

The placement process employs a complex parallel branch-and-bound (B&B) method. Starting from the root node of the tree, a depth-first search systematically explores potential solutions. During this process, the algorithm assigns rotation nodes with specified directions (north, south, east, west) and determines partial or complete sequence pairs for chiplet arrangement.

Figure 3: Comparison of SP-Tree and CSP-Tree structures, demonstrating the more efficient organization of the SP-Tree approach.

Analysis and Optimization of White Spaces

The whitespace optimization process consists of four steps. First, the system processes virtual chiplet movement, allowing initial position optimization without considering physical constraints. Second, individual chiplet optimization adjusts each component to achieve the best placement.

In the third step, fixed and free chiplet movement strategies are introduced, where some chiplets remain stationary while others are repositioned. Finally, the system executes multi-chiplet group optimization, simultaneously considering the collective movement of multiple components. This hierarchical approach ensures a comprehensive exploration of space.

Figure 4: Sequential optimization steps illustrating different chiplet movement and whitespace utilization methods.

Post-Placement Thermal Considerations

The thermal optimization phase employs precise thermal management techniques. The system uses a 64×64×5 grid for thermal simulation, providing an accurate temperature distribution model for the entire design. The temperature calculations leverage the SuperLU 5.3.0 matrix solver to ensure efficient and precise thermal analysis.

The optimization process implements two different movement strategies: the first strategy focuses on the movement of a single chiplet within the calculate allowable region, while the second strategy considers the coordinated movement of entire chiplet groups. These complementary approaches help address local hotspots and overall thermal distribution.

Figure 5: Thermal optimization methods demonstrating single chiplet and entire chiplet group movement strategies.

Experimental Results

The system was implemented in C/C++ and tested on a Linux workstation equipped with an Intel Xeon processor. The results showed significant improvements in performance of metrics and processing efficiency. In terms of routing length optimization, the system achieved up to a 1.035% improvement in total routing length compared to existing methods, with a 156× increase in processing speed.

The thermal performance results were equally remarkable, achieving up to an 8.214°C temperature reduction while maintaining reasonable routing length metrics. In most test cases, the system successfully met the 85°C temperature constraint with only a 5.376% average increase in routing length.

Figure 6: Temperature distribution diagrams demonstrating thermal improvements under different placement configurations.

Conclusion

The SP-Tree based placement method, combined with thermal considerations, represents a significant advancement in 2.5D integrated circuit design. This framework successfully integrates efficient combinatorial search techniques with practical thermal management strategies, forming a theoretically sound and practical solution.

The system performs particularly well when handling designs with around ten or fewer chiplets, aligning closely with current industrial demands. By effectively balancing routing length optimization and thermal constraints, this framework provides a comprehensive solution for modern 2.5D integrated circuit implementations.

References

[1] H.-W. Chiou, J.-H. Jiang, Y.-T. Chang, Y.-M. Lee, and C.-W. Pan, "Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration," National Yang Ming Chiao Tung University, Jan. 17, 2023.