Designing High-Efficiency and Fabrication-Tolerant Bi-Layer Grating Couplers for Silicon Photonics

Introduction

Silicon photonics, which leverages the well-established CMOS fabrication processes, has emerged as a promising platform for realizing highly integrated optical circuits. The most widely adopted platform is Silicon-On-Insulator (SOI), where the high refractive index contrast between the silicon core and silicon dioxide cladding enables tightly confined optical waveguides. However, the significant mode size mismatch between these nanoscale SOI waveguides and standard single-mode fibers presents a formidable challenge for efficient fiber-to-chip coupling.

Grating couplers (GCs) have gained widespread adoption as a solution for fiber-to-chip coupling in silicon photonics due to their wafer-scale compatibility, relaxed fiber alignment tolerances, and the ability to be integrated anywhere on the chip surface. While GCs with metal back-reflectors embedded in the substrate can achieve high coupling efficiencies, their fabrication can be challenging and may require non-CMOS-compatible materials.

This tutorial article presents a strategy for designing highly efficient and fabrication-tolerant bi-layer GCs for a 220 nm thick SOI platform. By introducing an apodized amorphous silicon (a-Si) or amorphous germanium (a-Ge) top layer, coupling efficiency values exceeding –0.3 dB can be numerically demonstrated.

Bi-Layer Grating Coupler Layout

The proposed bi-layer GC design, as illustrated in Figure 1(a), consists of a bottom layer with a thickness of 220 nm and an etching depth of 110 nm, serving as the light guiding layer. On top of this layer, separated by a 20 nm silicon dioxide spacer, is a fully etched top layer with varying thickness (a-Si or a-Ge).

Both the bottom and top layers feature linearly apodized fill factors, with opposite signs for the apodization functions. Additionally, the grating period is recalculated for each scattering element to satisfy the Bragg condition along the entire GC length. A minimum feature size of 60 nm, compatible with electron-beam lithography, is employed.

Fig. 1. (a) Schematic of the bi-layer grating coupler (GC); (b) 3D-FDTD simulation results for coupling efficiency (CE) across wavelengths for single-layer and bi-layer GCs. Parameters for single-layer: Rbot = 0.0275 µm^-1, zf = 6.2 µm, T = 700 nm. Bi-layer with a-Si overlay: htop = 100 nm, Rbot = 0.0291 µm^-1, Rtop = 0.0221 µm^-1, zf = 6.5 µm, T = 540 nm. Bi-layer with a-Ge overlay: htop = 77 nm, Rbot = 0.0322 µm^-1, Rtop = 0.0167 µm^-1, zf = 6.5 µm, T = 550 nm. Other specs include: hbot = 220 nm, e = 110 nm, B = 2 µm, θ = 14.5°, s = 20 nm, Fin,bot = 0.9, Fin,top = 0.1, GC width = 14 µm.

Numerical Simulations and Results

The GC design process involved two steps. First, only the bottom layer was considered, and its coupling efficiency at 1550 nm was optimized using 2D-FDTD simulations by sweeping over the etching depth, bottom linear apodization factor, and fiber-to-grating distance parameters. A subsequent 3D-FDTD simulation of the optimized single-layer GC yielded a peak coupling efficiency of –1.67 dB at 1550 nm and a 1dB bandwidth of 34.8 nm, as shown in Figure 1(b).

In the second step, a top layer (a-Si or a-Ge) was introduced, and particle swarm optimization was performed on the parameter space, including the top layer thickness, apodization factors, and fiber-to-grating distance. The optimized bi-layer GC with an a-Si overlay achieved a peak coupling efficiency of –0.29 dB and a 1dB bandwidth of 32.2 nm at 1550 nm, while the a-Ge overlay variant exhibited a peak coupling efficiency of –0.27 dB and a 1dB bandwidth of 32.4 nm, as depicted in Figure 1(b).

Fabrication Tolerance Analysis

The sensitivity of the bi-layer GCs to fabrication errors was evaluated by investigating the dependence of the peak coupling efficiency on variations in the top layer thickness and the layer misalignment in the propagation direction, which may result from mask misalignment during lithography.

As illustrated in Figure 2(a), the a-Si overlay GC demonstrated better tolerance to top layer thickness variations compared to the a-Ge variant, owing to its lower refractive index and larger dimensions. Both designs exhibited relaxed fabrication tolerance to layer misalignment, as shown in Figure 2(b).

Fig. 2. GC sensitivity to critical fabrication parameters: CE1550 dependence on (a) top thickness htop variation and (b) layer misalignment.

Conclusion

In summary, this tutorial article presented a strategy for designing highly efficient bi-layer GCs based on the use of either an a-Si or an a-Ge overlay for a 220 nm thick SOI platform. Numerical simulations demonstrated peak coupling efficiency values greater than –0.3 dB with 1dB bandwidths wider than 32 nm in the telecommunications C-band for both approaches. The a-Si overlay GC exhibited better fabrication tolerance in terms of the overlay thickness, while both designs showed relaxed fabrication tolerance to layer misalignment.

The proposed bi-layer GC designs offer a promising solution for efficient and robust fiber-to-chip coupling in silicon photonic integrated circuits, enabling high-performance optical interconnects for various applications ranging from telecommunications to sensing and computing.

Reference

[1] V. Vitali, C. Lacava, T. Domínguez Bucio, I. Cristiani, F. Gardes, and P. Petropoulos, "Design of Sub-Decibel-Loss and Fabrication-Tolerant Silicon Photonic Bi-Layer Grating Couplers," Optoelectronics Research Centre, University of Southampton, Southampton, UK, and Department of Electrical, Computer and Biomedical Engineering, University of Pavia, Pavia, Italy, 2024.