Enabling Direct-Drive 224 Gbps/λ PAM4 and 112 Gbps/λ NRZ Transmission with FOWLP Electronic-Photonic Integration

Introduction

The ever-increasing demand for energy-efficient and low-latency optical interconnects in AI/ML clusters and hyperscale data centers has led to the exploration of co-packaged optics (CPO) as a promising solution. Among various CPO architectures, the direct-drive approach, where the drivers are integrated within the (Switch) ASIC Serdes, stands out as the most energy-efficient option. However, implementing direct-drive poses significant challenges, including laser integration/disintegration, Photonic Integrated Circuit (PIC) performance, Optical Engine (OE) footprint and channel density, and electronic-photonic integration.

FOWLP: A Key Enabler for Electronic-Photonic Integration

Fan-Out Wafer Level Packaging (FOWLP) is a low-cost and mature advanced packaging technology that has found widespread use in electronics. By leveraging FOWLP for electronic-photonic integration, it is possible to address several challenges associated with direct-drive implementation. This approach enables PIC chiplet embedding, electrical interconnection without wire bonds, and exposure of optical ports on both PIC surface and edges for optical coupling.

Fabrication Process

The fabrication process begins with silicon PIC wafer fabrication and wafer-level testing to identify Known Good Dies (KGDs). These KGDs are then reconstituted into wafers for packaging using FOWLP. The DC and RF interconnects are realized using Front-side (F) and Back-side (B) Re-distribution Layers (RDLs) in conjunction with Through Mold Vias (TMVs). The completed OE packages are subsequently singulated and assembled onto organic substrates using C4 bumps. Figure 1 illustrates the direct-drive configuration, where the OEs and ASIC are interconnected using substrate RDLs. The package interconnect comprises substrate RDL (2 mm), bump, TMV, and FRDL (3.2 mm), as shown in Fig. 1(b). Notably, the RF insertion loss of this interconnect was less than 1.5 dB, even up to 67 GHz, as depicted in Fig. 1(c).

Fig. 1: (a) Illustration of a FOWLP-packaged silicon photonic transmitter with optional flip-chip attachment for TIAs in receivers (not covered in this work). (b) RF signals transmitted via interconnects including substrate RDL (2 mm), bump, TMV, and FRDL (3.2 mm). (c) RF insertion loss measured from S21 data for the complete RF interconnect

Results and Discussion

112 GBaud NRZ (112 Gbps/λ) Transmission:

The transmission performance of 112 GBaud NRZ was evaluated, and the results demonstrated that even with the direct-drive configuration (through the package RF interconnect), good Transmitter and Dispersion Eye Closure (TDEC) could be achieved, even without receive-side equalization, as shown in Fig. 2.

Fig. 2: (a) 112 GBaud NRZ (112 Gbps) eye diagram without receive-side equalization. (b) Eye diagram after applying a 5-tap FFE on the receive side. (c) TDEC performance relative to the number of receive-side FFE taps, showing strong TDEC even without equalization.

112 GBaud PAM4 (224 Gbps/λ) Transmission:

For 112 GBaud PAM4 transmission, the direct-drive configuration required approximately twice as many FFE taps to achieve the same TDECQ (Transmitter Dispersion Eye Closure Quaternary) performance as the directly-probed TWMZM (Traveling Wave Mach-Zehnder Modulator). This is largely due to impedance discontinuities at the various interfaces of the package RF interconnect components, as shown in Fig. 3.

Fig. 3: 112 GBaud PAM4 (224 Gbps) eye diagrams post-receive-side equalization with (a) 5-tap FFE and (b) 21-tap FFE. (c) TDECQ plotted against the number of receive-side FFE taps, highlighting the need for additional taps to address signal impairments in a direct-drive setup involving substrate RDL, bump, TMV, and FRDL.

However, after transmit-side FFE taps optimization, an outer ER (Extinction Ratio) of 4.277 dB was obtained, and a TDECQ of 2.32 dB was achieved after receive-side 21-tap FFE, demonstrating the feasibility of direct-drive for 224 Gbps PAM4 with FOWLP OEs, as illustrated in Fig. 4.

Fig. 4: 112 GBaud PAM4 (224 Gbps) eye diagram following optimization with transmit-side FFE taps. Achieved an outer ER of 4.277 dB and TDECQ of 2.32 dB using 21-tap FFE, demonstrating the viability of direct-drive.

Conclusion

The successful demonstration of 112 Gbps NRZ and 224 Gbps PAM4 transmission for direct-drive silicon photonic OEs fabricated using the FOWLP electronic-photonic integration platform paves the way forward for low-cost, low-power, and low-latency CPO solutions. While some challenges related to impedance discontinuities were observed, these can be addressed through further RF design optimization, highlighting the potential of this approach for future high-performance optical interconnects in AI/ML clusters and hyperscale data centers.

Reference

[1] X. Li, S. B. Nair Gourikutty, J. Wu, T. G. Lim, J. C. Davies, E. S. C. Koh, L. B. Long, C. S. Choong, S. Sandra, S. Bhattacharya, and J. T.-Y. Liow, "Direct-Drive 224 Gbps/λ PAM4 and 112 Gbps/λ NRZ Silicon Photonic Transmitter Enabled by FOWLP Electronic-Photonic Integration," in IEEE SiPhotonics, 2024.